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LH52D1000
FEATURES * Access time: 85 ns (MAX.), 100 ns (MAX.) * Current consumption: Operating: 40 mA (MAX.) 6 mA (MAX.) (tRC, tWC = 1 s) Standby: 45 A (MAX.) * Data Retention: 1.0 A (MAX. VCCDR = 3 V, tA = 25C) * Single power supply: 2.7 V to 3.6 V * Operating temperature: -40C to +85C * Fully-static operation * Three-state output * Not designed or rated as radiation hardened * Packages: 32-pin 8 x 20 mm2 TSOP 32-pin 8 x 13.4 mm2 STSOP * N-type bulk silicon DESCRIPTION
The LH52D1000 is a static RAM organized as 131,072 x 8 bits which provides low-power standby mode. It is fabricated using silicon-gate CMOS process technology.
A11 A9 A8 A13 WE CE2 A15 VCC NC A16 A14 A12 A7 A6 A5 A4
CMOS 1M (128K x 8) Static Ram
PIN CONNECTIONS
32-PIN TSOP 32-PIN STSOP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 TOP VIEW
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
OE A10 CE1 I/O8 I/O7 I/O6 I/O5 I/O4 GND I/O3 I/O2 I/O1 A0 A1 A2 A3
52D1000S-1
Figure 1. Pin Connections for TSOP and STSOP Packages
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LH52D1000
CMOS 1M (128K x 8) Static RAM
17 A4 16 A5 15 A6 14 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 13 3 2 31 1 12 4 11 7 10 ADDRESS BUFFER
A0 A1 A2 A3
20 19 18 10 1024 ROW DECODER MEMORY CELL ARRAY (1024 x 128 x 8)
8 VCC 24 GND
128 x 8 7 COLUMN DECODER 128
COLUMN GATE
8 CE CONTROL LOGIC
CE1 30 CE2 6
WE 5 OE 32
OE, WE CONTROL LOGIC
I/O BUFFER
21 22 23 25 26 27 28 29 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8
52D1000S-2
Figure 2. LH52D1000 Block Diagram
PIN DESCRIPTION
SIGNAL PIN NAME SIGNAL PIN NAME
A0 - A16 CE1 CE2 WE OE
Address inputs Chip enable 1 Chip enable 2 Write enable Output enable
I/O1 - I/O8 VCC GND NC
Data inputs and outputs Power supply Ground No connection
2
CMOS 1M (128K x 8) Static RAM
LH52D1000
TRUTH TABLE
CE1 CE2 WE OE MODE I/O1 - I/O8 SUPPLY CURRENT NOTE
H L L L
L H H H
L H H
L H
Standby Write Read Output disable
High impedance Data input Data output High impedance
Standby (ISB ) Active (ICC) Active (ICC) Active (ICC)
1 1
NOTE: 1. = Don't care L = Low H = High
ABSOLUTE MAXIMUM RATINGS
PARAMETER SYMBOL RATING UNIT NOTE
Supply voltage Input voltage Operating temperature Storage temperature
VCC VIN TOPR TSTG
-0.3 to +4.6 - 0.3 to VCC + 0.3 -40 to +85 -55 to +1 50
V V C C
1 1, 2
NOTE: 1. The maximum applicable voltage on any pin with respect to GND. 2. Undershoot of -3.0 V is allowed width of pulse below 50 ns.
RECOMMENDED DC OPERATING CONDITIONS (TA = -40C to +85C)
PARAMETER SYMBOL MIN. TYP. MAX. UNIT NOTE
Supply voltage Input voltage
VCC VIH VIL
2.7 2.0 -0.3
3.0
3.6 VCC + 0.3 0.6
V V V
1
NOTE: 1. Undershoot of -3.0 V is allowed width of pulse below 50 ns.
DC ELECTRICAL CHARACTERISTICS (TA = -25C to +85C, VCC = 2.7 V to 3.6 V)
PARAMETER SYMBOL CONDITIONS MIN. TYP. MAX. UNIT
Input leakage current Output leakage current Operating supply current Standby current Output voltage
ILI
VIN = 0 to VCC CE1 = VIH or CE2 = VIL or OE = VIH or WE = VIL VI/O = 0 V to VCC VIN = VIL or VIH, CE1 = VIL, WE = V IH CE2 = VIH, II/O = 0 mA CE1 = 0.2 V, VIN = 0.2 V or VCC - 0.2 V CE2, WE = VCC - 0.2 V, II/O = 0 mA CE1 = VCC - 0.2 V or CE2 = 0.2 V CE1 = VIH or CE2 = VIL IOL = 2.1 mA IOH = -0.5 mA tCYCLE = Min tCYCLE = 1.0 s
-1.0
1.0
A
ILO ICC ICC1 ISB ISB1 VOL VOH
-1.0 VCC - 0.5

1.0 40
A
mA 6 45 2.0 0.4 A mA V V
3
LH52D1000
CMOS 1M (128K x 8) Static RAM
AC ELECTRICAL CHARACTERISTICS AC Test Conditions
PARAMETER MODE NOTE
Input pulse level Input rise and fall time Input and output timing Ref. level Output load
NOTE: 1. Including scope and jig capacitance.
0.4 V to 2.4 V 5 ns 1.5 V 100 pF + 1TTL
1
READ CYCLE (TA = -40C to +85C, VCC = 2.7 V to 3.6 V)
PARAMETER SYMBOL MIN. MAX. UNIT NOTE
Read cycle time Address access time CE 1 access time CE 2 access time Output enable to output valid Output hold from address change CE 1 Low to output active CE 2 High to output active OE Low to output active CE 1 High to output in High impedance CE 2 Low to output in High impedance OE High to output in High impedance
tRC tAA tACE1 tACE2 tOE tOH tLZ1 tLZ2 tOLZ tHZ1 tHZ2 tOHZ
85 10 5 5 0 0 0 0 85 85 85 45 35 35 35
ns ns ns ns ns ns ns ns ns ns ns ns
1 1 1 1 1 1
NOTE: 1. Active output to High impedance and High impedance to output active tests specified for a 200 mV transition from steady state levels into the test load.
WRITE CYCLE (TA = -40C to +85C, VCC = 2.7 V to 3.6 V)
PARAMETER SYMBOL MIN. MAX. UNIT NOTE
Write cycle time CE 1 Low to end of write CE 2 High to end of write Address setup time Write pulse width Write recovery time Input data setup time Input data hold time WE High to output active WE Low to output in High impedance OE High to output in High impedance
tWC tCW1 tCW2 tAS tWP tWR tDW tDH tOW tWZ tOHZ
85 75 75 0 60 0 35 0 0 0 0
35
ns ns ns ns ns ns ns ns ns ns ns
1 1 1
NOTE: 1. Active output to High impedance and High impedance to output active tests specified for a 200 mV transition from steady state levels into the test load.
4
CMOS 1M (128K x 8) Static RAM
LH52D1000
DATA RETENTION CHARACTERISTICS (TA = -40C to +85C)
PARAMETER SYMBOL CONDITIONS MIN. TYP MAX. UNIT NOTE
Data retention supply voltage
VCCDR
CE2 0.2 V or CE1 VCCDR - 0.2 V VCCDR = 3.0 V CE2 0.2 V or CE1 VCCDR - 0.2 V TA = 25C TA = 40C
2.0

3.6 1.0 3.0 35
V
1
Data retention supply current
ICCDR
A
1
Chip enable setup time Chip enable hold time
tCDR

0
ms

tR
5
ms
NOTE: 1. CE2 VCCDR - 0.2 V or CE2 0.2 V 2. Typical values at TA = 25C
PIN CAPACITANCE (TA = 25C, f = 1 MHz)
PARAMETER SYMBOL CONDITIONS MIN. TYP. MAX. UNIT NOTE
Input capacitance I/O capacitance
CIN CI/O
VIN = 0 V VI/O = 0 V

10 10
pF pF
1 1
NOTE: 1. This parameter is sampled and not production tested.
5
LH52D1000
CMOS 1M (128K x 8) Static RAM
tRC
ADDRESS tAA tACE1
CE1 tLZ1 tHZ1
CE2 tLZ2 tACE2 tOE tHZ2
OE tOLZ tOHZ tOH
DOUT NOTE: WE is HIGH for Read cycle.
DATA VALID
52D1000S-3
Figure 3. Read Cycle
6
CMOS 1M (128K x 8) Static RAM
LH52D1000
tWC
ADDRESS
OE tCW
(NOTE 2)
(NOTE 4)
tWR
CE1 tCW
(NOTE 2)
tWR
CE2 tAS
(NOTE 3)
tWP
(NOTE 1)
tWR
WE tOHZ
(NOTE 6)
DOUT tDW
(NOTE 5)
tDH
DIN NOTES: 1. A write occurs during the overlap of a LOW CE1, a HIGH CE2 and a LOW WE. A write begins at the latest transition among CE1 going LOW, CE2 going HIGH and WE going LOW. A write ends at the earliest transition among CE1 going HIGH, CE2 going LOW and WE going HIGH. tWP is measured from the beginning of write to the end of write. 2. tCW is measured from the later of CE1 going LOW or CE2 going HIGH to the end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end of write to the address change. tWR1 applies in case a write ends at CE1 or WE going HIGH. tWR2 applies in case a write ends at CE2 going LOW. 5. During this period, I/O pins are in the output state, therefore the input signals of opposite phase to the outputs must not be applied. 6. If CE1 goes LOW simultaneously with WE going LOW or after WE going LOW, the outputs remain in high impedance state. 7. If CE1 goes HIGH simulaneously with WE going HIGH or before WE going HIGH, the outputs remain in high impedance state.
DATA VALID
52D1000S-4
Figure 4. Write Cycle (OE Controlled)
7
LH52D1000
CMOS 1M (128K x 8) Static RAM
tWC
ADDRESS tCW
(NOTE 2)
tWR
(NOTE 4)
CE1 tCW
(NOTE 2)
tWR
CE2 tAS
(NOTE 3)
tWP
(NOTE 1)
tWR
WE tWZ tOW
(NOTE 7)
(NOTE 6)
DOUT tDW DIN
(NOTE 5)
tDH
DATA VALID
NOTES: 1. A write occurs during the overlap of a LOW CE1, a HIGH CE2 and a LOW WE, A write begins at the latest transition among CE1 going LOW, CE2 going HIGH and WE going LOW. A write ends at the earliest transition among CE1 going HIGH. CE2 going LOW and WE going HIGH. tWP is measured from the beginning of write to the end of write. 2. tCW is measured from the later of CE1 going LOW or CE2 going HIGH to the end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end of write to the address change. tWR1 applies in case a write ends at CE1 or WE going HIGH. tWR2 applies in case a write ends at CE2 going LOW. 5. During this period, I/O pins are in the output state, therefore the input signals of opposite phase to the outputs must not be applied. 6. If CE1 goes LOW simultaneously with WE going LOW or after WE going LOW, the outputs remain in high impedance state. 7. If CE1 goes HIGH simulaneously with WE going HIGH or before WE going HIGH, the outputs remain in high impedance state.
52D1000S-5
Figure 5. Write Cycle (OE Low Fixed)
8
CMOS 1M (128K x 8) Static RAM
LH52D1000
CE1 CONTROL (NOTE)
DATA RETENTION MODE VCC 2.7 V 2.2 V VCCDR CE1 VCCDR - 0.2 V CE1 0V CE2 CONTROL tCDR tR
DATA RETENTION MODE VCC 2.7 V CE2 VCCDR 0.6 V tCDR tR
0V CE2 0.2 V NOTE: To control the data retention mode at CE1, fix the input level of CE2 between VCCDR and VCCDR - 0.2 V or 0 V to 0.2 V during the data retention mode.
52D1000S-6
Figure 6. Data Retention (CE1 Controlled)
9
LH52D1000
CMOS 1M (128K x 8) Static RAM
PACKAGE DIAGRAM
32TSOP (Type I) (TSOP032-P-0820)
0.30 [0.012] 0.10 [0.004] 32 0.50 [0.020] TYP. 17
18.60 [0.732] 18.20 [0.717]
20.30 [0.799] 19.70 [0.776]
19.00 [0.748]
1 8.20 [0.323] 7.80 [0.307]
16 0.20 [0.008] 0.10 [0.004] 1.10 [0.043] 0.90 [0.035] 1.20 [0.047] MAX. 0.425 [0.017] 0.20 [0.008] 0.00 [0.000]
0.15 [0.006]
DIMENSIONS IN MM [INCHES]
MAXIMUM LIMIT MINIMUM LIMIT
32TSOP
10
CMOS 1M (128K x 8) Static RAM
LH52D1000
32TSOP (TSOP032-P-0813)
0.08 [0.003] M
1
32 0.22 [0.009] 0.50 [0.020] 17
16 11.90 [0.468] 11.70 [0.461]
0.25 [0.010] TYP. 0.15 [0.006] 0.05 [0.002] 1.10 [0.043] 0.90 [0.035] 1.20 [0.047] MAX.
13.60 [0.535] 13.20 [0.520] SEE DETAIL DETAIL
0.20 [0.008] 0.90 [0.003] 0 - 10 0.60 [0.024] 0.40 [0.016] MAXIMUM LIMIT MINIMUM LIMIT
DIMENSIONS IN MM [INCHES]
8.40 [0.331] MAX.
8.10 [0.319] 7.90 [0.311]
0.10 [0.004]
32STSOP
11
LH52D1000
CMOS 1M (128K x 8) Static RAM
ORDERING INFORMATION
LH52D1000 Device Type X Package - ## Speed LL Power Low-Low power standby 10 100 Access Time (ns) 85 85 T 32-pin, 8 mm x 20 mm2 TSOP (TSOP32-P-0820) S 32-pin, 8 mm x 13 mm2 STSOP (STSOP32-P-0813) CMOS 1M (124K x 8) Static RAM Example: LH52D1000T-85LL (CMOS 1M (124K x 8) Static RAM, 85 ns, Low-Low power standby, 32-pin TSOP)
52D1000S-7
12

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